1. Field of the Invention
This invention relates to frequency divider circuits and particularly to high-speed frequency divider circuits.
2. Description of the Related Art
An exemplary phase-locked loop (PLL) (e.g., PLL 100 of FIG. 1) includes a frequency divider (e.g., frequency divider circuit 110) to divide down an output of a voltage controlled oscillator (e.g., VCO 108). For example, a divide-by-two circuit (e.g., frequency divider 200 of FIG. 2) includes a master-slave flip-flop with two D-latches in cascade and in a feedback configuration. The output of frequency divider 200 toggles after each input clock cycle, producing an output signal that toggles at a rate half of the rate of the input clock signal.
Frequency divider circuit 200 may be implemented using current mode logic (CML) blocks having a differential architecture biased by a substantially input independent tail current. A typical CML frequency divider (e.g., frequency divider 300 of FIG. 3) couples master latch 302 to slave latch 304. During a track mode, the tail current flows through devices 308 and during a latch mode, the tail current flows through devices 310. The devices of frequency divider 300 are sized such that in operation, frequency divider 300 self-oscillates with a natural frequency of oscillation (i.e., frequency divider 300 produces an output clock having the natural frequency when an input full-rate clock has a differential signal voltage of zero). The divider natural frequency of oscillation is a function of load resistor value (RL), latch small-signal transconductance (gm) value, and gate and wire capacitance.
As the voltage of the input clock differential signal is increased, the frequency divider experiences an “injection locking effect.” Due to injection of the full-rate input signal through devices 306, the frequency divider behaves as an oscillator with its output clock frequency pulled from the natural frequency to oscillate at a half-rate frequency of the input clock. Voltage Vmin is the minimum amplitude of the full-rate input clock signal (CLK minus CLKB) for which the frequency divider maintains lock, i.e., outputs a half-rate frequency signal for a particular full-rate input clock signal. In general, Vmin increases with increases in the deviation of the frequency of the full-rate input signal from twice the value of the divider natural frequency. The greater the full-rate input signal voltage, the farther away it can pull the frequency of the output signal of the divider from the natural frequency.
As the VCO frequency of oscillation rises, parasitic capacitance and resistance may reduce signal swing at the inputs of the frequency divider. For example, the output voltage swing of VCO 108 may be less than Vmin, preventing the frequency divider circuit from locking to the half-rate signal. Accordingly, improved techniques for dividing the frequency of an input clock signal are desired.